OpenAI unveiled Jalapeño on August 25, the company's first AI accelerator chip. It delivers up to 13.4 petaflops of 4-bit compute, accesses 232 gigabytes of memory at 15.4 terabytes per second, and reduces end-to-end latency by up to 3.6 times compared to Nvidia's GB300. The performance claims are significant. The more interesting story is how fast the chip went from concept to silicon, and what role OpenAI's own language models played in getting it there.

A 20-Month Timeline That Experts Call Best in Class

Jalapeño moved from first architecture concept to first silicon in under 20 months. Only nine months separated the first register-transfer level code from tape-out, when the finished design goes to manufacturing. Andrew Kahng, a distinguished professor at UC San Diego, called the speed "likely best in class today."

The team that built it averaged fewer than 100 people over the course of the project. That number spans system design, software, and supply chain, but excludes Broadcom, which partnered with OpenAI on physical design and implementation. OpenAI handled end-to-end system design including the inference accelerator, memory hierarchy, and networking. Broadcom took over from the gates onward, handling the physical layout, routing, and fabrication handoff.

David Chin, co-founder at agentic chip design startup Verkor.io, called the schedule credible but noted Broadcom's involvement was essential. "If you have somebody else start from scratch, it won't be possible," he said. The speed is real, but it came with a significant head start from an established implementation partner.

How LLMs Fit Into the Design Workflow

OpenAI built its front-end workflow around Accelerated Hardware Synthesis, or XLS, an open-source high-level synthesis toolchain originally developed at Google. XLS lets designers write chip logic in languages like DSLX, a domain-specific language inspired by Rust, and C++. The toolchain converts that code into Verilog, the hardware description language used to specify electronic systems.

Chris Leary, a member of technical staff at OpenAI who created XLS during his time at Google, said the team recognized early that AI models were better at tasks that looked like software. XLS sits in that sweet spot. The models could help write and refine high-level synthesis code because the input and output formats resembled programming rather than low-level hardware manipulation.

The models available to the team evolved over the project's duration. The work began with assistance from o3, which was released publicly in April 2025 but available to the Jalapeño team earlier. By the time the project wrapped up, the team had access to precursors of GPT-6 Astra, which did not ship publicly until September 3, 2026. The newer model can work directly in Verilog without needing XLS as an intermediary, and it is close to operating proprietary design tools on its own, according to Leary.

Ho confirmed the team also used internal LLMs fine-tuned for chip design that are not available to the public. He declined to specify which models, but said the goal is to fold lessons from Jalapeño into OpenAI's commercial offerings. "It's safe to say that Astra and following models will be very good at chip design," Ho said.

The Software Side Moves Fast

When the first chips returned from the foundry in May, the team pointed its internal AI models at the software problem. Writing efficient kernels for new hardware is typically a months-long process. On DeepSeek's multi-head latent attention kernel benchmark, the team went from 0.31 percent of theoretical peak performance to 88.94 percent in roughly 40 hours.

Ho said the result is repeatable, which has implications beyond Jalapeño. The time between foundry delivery and production ramp can shrink dramatically if AI can accelerate kernel optimization from weeks to days. "All our schedule assumptions are going to be based on the fact we have this capability now," Ho said.

The team pointed models at SemiAnalysis's InferenceX benchmark as well, working through the software stack that turns raw silicon performance into usable inference throughput. The first chips were not running production workloads. But the gap between first silicon and useful benchmarks is compressing.

Where AI Helped and Where It Did Not

The bulk of OpenAI's AI-assisted work focused on front-end design, the tasks from initial concept through RTL code and verification. At IEEE Hot Chips 2026, Ho and Leary presented numbers on AI-guided physical design optimization, including a 10 percent area reduction for matrix multiplication units compared to an optimized human baseline. That means AI-guided layout fit more circuits into the same silicon area.

But the deep backend work, routing interconnects, completing clock and power specifications, and preparing foundry deliverables, remained largely with Broadcom. The Jalapeño team includes physical design engineers who coordinate with Broadcom on floor planning and routing, but the most automation-resistant parts of the process did not see the same AI acceleration as the front end.

Ravi Krishna at Verkor said the approach feels conservative given how much models have improved since the project started in October 2024. "The models from the last four to five months have improved. From April onwards, is when they really started to be able to handle those tasks better," he said. The backend acceleration that was not practical for Jalapeño may be practical for the next chip.

What Comes Next

Ho and Leary hinted that Jalapeño's workflow may already look dated compared to what the team is building for the second generation. The first chip prioritized speed over innovation in the design process. "There's a trade-off between do we want to take time to do some innovation, or do we want to do things that we know work historically?" Leary said. "With the second generation, we have a kind of reset opportunity."

Ho said the second-generation workflow has "a lot of places that we are introducing" AI, including more work in verification and physical design. The team now has tools for automatic waveform manipulation and viewing, which automates analysis to identify clock signals associated with failures and improves debugging while the chip is still in design.

Both Ho and Leary were clear that full automation is not the goal. "We're not saying that anyone can come and just build state-of-the-art, frontier AI/ML accelerator chips using just Codex," Ho said. The claim is narrower: small teams using AI-augmented workflows can reach quality results on compressed timelines. Jalapeño is the proof point. The second chip will test whether the workflow scales.