CPython Now Runs on RISC-V, With More Performance Work on the Horizon
The CPython interpreter officially supports RISC-V as a Tier 3 platform, following an announcement on the Python Insider blog by contributor Stan Ulbrych. The milestone means RISC-V has been added to PEP 11, the document that defines which hardware platforms CPython guarantees support for, and marks the first time an open instruction set architecture has reached that status in the Python ecosystem.
RISC-V is an open-standard ISA designed as a royalty-free alternative to proprietary architectures like x86 and ARM. Its specification is modular and fully accessible, so any hardware vendor can implement it without paying licensing fees. The ecosystem has grown fast, with industry projections putting its market reach at four times its current size by 2032. Getting CPython working reliably on this hardware has been a priority for the language's maintainers for some time.
Months of Hardware Testing and Bug Fixes Got It Here
Reaching Tier 3 status in PEP 11 required extensive collaborative work. Contributors spent months running test suites on real physical RISC-V boards, fixing architecture-specific bugs, improving the build infrastructure, and reviewing patches. Ulbrych called out the RISE Project specifically for providing multiple RISC-V machines that served as buildbots, running automated tests and catching problems that only surface on actual silicon.
The RISE Project (RISC-V Software Ecosystem) is an industry consortium focused on upstreaming RISC-V support across major open-source projects. Their hardware contribution was essential, since cross-compilation and emulation can miss bugs that only appear when code executes on real RISC-V cores.
Tier 3 Means "It Works," But CI Feedback Is Still Slow
A Tier 3 designation in PEP 11 means the platform is officially recognized and supported, but breakage can happen without blocking a release. In practice, the buildbots that validate patches run only after code has already landed in the repository. That post-commit model introduces real latency when tracking down regressions, since a broken patch might sit in the tree for hours before anyone notices.
To close that gap, the team is partnering with the RISE Project on their RISE RISC-V Runners initiative. The goal is to plug RISC-V hardware directly into CPython's continuous integration pipeline, so tests run before patches merge rather than after. That shift from post-commit to pre-commit validation would give contributors much faster feedback on whether their changes work on RISC-V.
Tier 2 and Architecture-Specific Optimizations Are Next
Maintainers plan to push RISC-V toward Tier 2 status within PEP 11, which would require the platform to pass tests reliably enough that regressions block releases. Core contributors also want to investigate architecture-specific optimizations. Modern RISC-V cores support features like vector extensions (analogous to ARM's NEON or x86's AVX), bit manipulation instructions, and branchless execution patterns. Leveraging these capabilities could meaningfully improve Python interpreter performance on RISC-V hardware.
Hardware profiles like RV64GC (a 64-bit general-purpose RISC-V core with compressed instructions) and upcoming standards like RVA23 define the baseline feature set that software can rely on. As these profiles solidify, compiler and interpreter authors will have clearer targets for optimization.
The Ecosystem Needs More Than Just CPython
CPython is one layer of a much larger stack. Full RISC-V viability depends on third-party Python packages, compilers, toolchains, and developer tools all working reliably on the architecture. Ulbrych emphasized that community contributions across these layers will determine how quickly RISC-V becomes a practical platform for Python developers.
The development team has put out an explicit call for testing. Anyone with access to RISC-V hardware is encouraged to build CPython, run their workloads and test suites, and report what breaks. Real-world testing across diverse hardware and software configurations is the fastest way to surface the remaining issues.
Community reaction on Hacker News and Reddit's RISCV community was broadly positive, with developers treating the announcement as a sign of growing maturity. Discussions focused on the practical implications of Tier 3 status: official upstream support removes a significant friction point for teams that want to include RISC-V in their CI/CD pipelines, even if the platform can still occasionally break without blocking releases. The conversation also touched on how RISC-V's open model avoids the vendor lock-in and licensing restrictions that come with x86 and ARM, making it an increasingly attractive target for long-term investment.